The present invention relates to a semiconductor memory device. More particularly, the present invention relates to an improvement of a semiconductor memory device such as an internal synchronization static RAM.
2. Description of the Prior Art
An internal synchronization static RAM is known for example by the paper "16K static RAM takes new route to high speed" by Rahul Sud and Kim C. Hardee in Electronics/September 11, 1980 PP. 117-123.
FIG. 1 is a block diagram showing a construction of a conventional internal synchronization static RAM. First, referring to FIG. 1, a conventional internal synchronization static RAM will be described. Address signals A.sub.1 to A.sub.N are applied to input buffers 1l to 1N. A chip selection input signal CSext is applied to a CS buffer 2, from which a chip selection signal CS is commonly applied to the above stated input buffers 1l to 1N.
The input buffers 1l to 1N constitute a NOR circuit for receiving the address signals and the chip selection signal CS. The outputs of the input buffers 1l to 1N are applied to address transition detector circuits (referred to hereinafter as ATD circuits) 3l to 3N, respectively. The ATD circuits 3l to 3N generate a one-shot pulse signal according to a level change in the address signals A.sub.1 to A.sub.N. The one-shot pulse signal provided from the ATD circuits 3l to 3N is supplied to a NOR circuit 4.
The NOR circuit 4 comprises MOS field-effect transistors 4l to 4N and a load device 40. More specifically, the respective gate inputs of the MOS field effect transistors 4l to 4N are connected to the outputs of the ATD circuits 3l to 3N, the respective sources thereof are connected to the grounding potential and the respective drains thereof are connected commonly to the input of the inverter 5. Between the input of the inverter 5 and the power supply potential V.sub.cc, the load device 40 is connected. The load device 40 comprises for example a circuit including in series a MOS field-effect transistor and a resistor. The inverter 5 is formed by an enhancement-enhancement arrangement or enhancement-depletion arrangement of n channel MOS field effect transistors or by CMOS transistors.
FIGS. 2(a)-2(j) represent an operation timing chart of the conventional semiconductor memory device shown in FIG. 1. Referring to FIGS. 1 and 2(a)-2(j), the operation of the conventional semiconductor memory device will be described in the following. First, as shown in FIG. 2(b), the chip is enabled when the chip selection inputsignal CXext is at a low level. Then, as shown in FIG. 2(a), when the level of any of the address signals A.sub.1 to A.sub.N is changed, there is ia change in the output corresponding to the address signal having the changed level, from the input buffers 1l to 1N. Subsequently, out of the ATD circuits 3l to 3N, the one corresponding to the input buffer having the output changed generates a one-shot pulse signal ATDi as shown in FIG. 2(c). When the one-shot pulse signal ATDi is supplied from any one of the ATD circuits 3l to 3N to the NOR circuit 4, an ATD signal as shown in FIG. 2(d) is supplied to the inverter 5. The inverter 5 inverts the polarity of the ATD signal and provides an ATD signal as shown in FIG. 2(e). The ATD signal falls rapidly but rises slowly as shown in FIG. 2(d), because the rise is made by storage in the load device 40 connected between the power supply potential V.sub.cc and the input of the inverter 5. The ATD signal thus generated serves as a basic clock signal for controlling the operation time of a peripheral circuit such as a sense amplifier or a bit line load, not shown.
Then, when the chip selection input signal CSext is changed from the high level to the low level as shown in FIG. 2(f), all the outputs of the input buffers 1l to 1N are changed from the high level to the low level. At the time of the change from the high level to the low level of the chip selection input signal CSext, the chip selection input signal CSext is delayed by the CS buffer 2, so that a chip selection signal CS as shown in FIG. 2(g) is supplied with a change from the high level to the low level. Then, with a delay corresponding to the delay of the signal CSext, the outputs of the ATD circuits 3l to 3N are changed so that the ATD signal shown in FIG. 2(jis delayed by a period corresponding to the delay by the CS buffer 2.
Thus, in the conventional semiconductor memory device constructed as shown in FIG. 1, as a result of the delay of the chip selection input signal CSext by the CS buffer 2, the ATD signal is delayed by the time t shown in FIG. 2. In other words, the conventional semiconductor memory device has a disadvantage that the access by the chip selection input signal CSext is delayed compared with the access by the address signal A.sub.1 to A.sub.N.